1. Field of the Invention
The present invention generally relates to an automatic arrangement of wiring patterns in semiconductor device. More specifically, the present invention is directed to an automatic arrangement of wiring patterns in semiconductor device in high integration while omitting step of confirming interference occurred in wiring patterns inside and outside function blocks.
2. Description of the Related Art
As known in the method of automatically arranging and wiring patterns of semiconductor device, function blocks are called as xe2x80x9chardware-based coresxe2x80x9d, or xe2x80x9ccoresxe2x80x9d simply, and these cores are arranged in a semiconductor device such as a gate array. A core is designed by a combination of function cells and a primitive made of a plurality of function cells. In connection with multi-functions of a core, very recently, a total number of terminals of the core is increased. The total number of terminals may mainly influence the size of the core. Function blocks of a semiconductor device are arranged and wired by utilizing a computer.
Referring now to the drawings, a conventional automatic arranging and wiring method of a semiconductor device containing a core (related art 1) will be described. FIG. 1 is a flow chart for describing the conventional automatic arranging and wiring method as the related art 1. FIG. 2A is a plan view for representing setting of a boundary line of a core in accordance with the related art 1 of FIG. 1. FIG. 2B is an enlarged plan view for showing the vicinity of the boundary line (inside circle) of the core indicated in FIG. 2A. Also, FIG. 3 is a plan view for representing the core arranging and wiring patterns, corresponding to FIG. 2A, formed by the conventional arranging and wiring method as the related art 1.
Referring now to the flow chart of FIG. 1, the automatic arranging and wiring method of the related art 1 will be explained.
At a step S20, an optimum size of a core is set based upon a circuit scale of the core. As indicated in FIG. 2A, a boundary line 12 is set for a region (an automatic layout region) where an automatic layout process is performed to a cell array region 11.
Next, at a step S21, a function cell 18 inside the core is an interface with an external circuit outside the core. The function cell 18 is arranged inside the automatic layout region set at the step S20 such that the function cell (the interface function cell) 18 is located adjacent to the boundary line 12.
In this case, this is because the designing flexibility of internal wiring lines (corresponding to wiring lines indicated by reference numeral 17 shown in FIG. 3) arranged in the core is increased, when the internal wiring lines are automatically designed by using a computer.
Subsequently, at a step S22, the internal wiring lines 17 are automatically arranged and wired by using an automatic arranging and wiring program in which data related to the plurality of interface function cells 18 has been entered. At this time, as indicated in FIG. 3, each of the internal wiring lines 17 is connected to the plurality of interface function cells 18.
Next, at a step S23, with reference to the automatic arranging and wiring result of the core formed at the step S22, a judgment is made whether or not a wiring line region xe2x80x9cKxe2x80x9d is reserved between the boundary line 12 and all of the terminals 19 of the interface function cells 18. In this case, the wiring line region xe2x80x9cKxe2x80x9d is used to arrange wiring lines (external wiring lines, not shown in detail) connected to external circuits outside the core. In other words, a confirmation is made that any of the internal wiring lines 17 are not present between the terminals 19 and the boundary line 12.
When it is so judged that the wiring line region K is not reserved between all of the terminals 19 of the interface function cells 18 and the boundary line 12, the automatic arranging and wiring operation of the core corresponding to the step S22 is again performed. Otherwise, the automatic arranging and wiring result of the core generated at the step S22 is manually corrected.
If the result of the judgment at the step S23 is desired, then the judged automatic arranging and wiring result is outputted as layout data. It should be understood that since, in FIG. 3, the wiring region K is reserved between all of the terminals 19 and the boundary line 12, FIG. 3 schematically represents this automatic arranging and wiring result judged as a xe2x80x9cdesiredxe2x80x9d result at the step S23.
As a consequence, the terminals 19 corresponding to the automatic arranging and wiring result outputted as the layout data can be terminals which are directly connectable with the external wiring lines without causing shortcircuits with the internal wiring lines 17.
However, in the above-described related art 1, in case that the wiring region K near the boundary line 12 cannot be reserved, the automatic arranging and wiring operation must be repeatedly performed. Otherwise, the correcting work is required, resulting in lowering of the design efficiency.
To avoid this problem, another related art about automatic arranging and wiring method has been proposed with using a virtual block as a terminal portion of a core.
This conventional designing method (namely, related art 2) will now be explained with reference to FIG. 4 to FIG. 7. FIG. 4 is a flow chart for describing the conventional automatic arranging and wiring method as the related art 2.
FIG. 5A is a plan view for representing setting of the boundary line of the core in the related art 2, similar to FIG. 2A. FIG. 5B is an enlarged plan view for showing the vicinity of the boundary line of the core indicated in FIG. 5A, similar to FIG. 2B. FIG. 6 is a plan view for representing a layout formed by the conventional arranging and wiring method as the related art 2, similar to FIG. 3. FIG. 7A is a schematic circuit diagram for indicating a subject circuit for the conventional automatic arranging and wiring method of FIG. 4. FIG. 7B is a circuit diagram formed by inserting a virtual block into the schematic circuit diagram shown in FIG. 7A.
As indicated in FIG. 4 and FIG. 7A, at a first step S25 of FIG. 4, a position of an external terminal 8 outside a core is predicted, and a virtual block 32 is inserted between this predicted external terminal 8 and a function cell 28 to be an interface of the core. This condition is indicated in FIG. 7B. In FIG. 7A and FIG. 7B, symbol xe2x80x9cHxe2x80x9d indicates a group of function cells arranged inside a boundary line 12 of the core except for the plurality of function cells 28.
At a next step S26, a position of a terminal 31 of the virtual block 32 is determined.
At a next step S27, an optimum size of the core is determined based upon a circuit scale of the core, and the boundary line 12 which marks a region for an automatic layout is set, as shown in FIG. 5A.
Next, at a step S28, the virtual block 32 shown in FIG. 5B is arranged adjacent to the boundary line 12 of the core. In this case, a size of this virtual block 32 is defined based upon a single cell of a minimum unit cell (corresponding to a minimum rectangular shape surrounded by a broken line in FIG. 5B) in the core. The terminal 31 of the virtual block 32 is set within the virtual block 32.
At a next step S29, an operation of automatically arranging and wiring internal wiring lines 17 of the core is performed by utilizing an automatic arranging and wiring program in which the condition defined at the step S28 is entered.
At a further step S30, the automatic arranging and wiring result of the core formed at the step S29 is outputted as layout data of the core shown in FIG. 6. As a consequence, the terminal 31 connected to the internal wiring line 17 becomes a terminal to be an interface of the core.
Different from the first-mentioned related art 1, the second related art 2 has the following merits. The region where no virtual block 32 is provided is present in a region located adjacent to the boundary line 12, and this region can be effectively used. As a result, the resultant core can be made more compact than that realized by the related art 1.
However, the conventional automatic arranging and wiring methods still have such a drawback that a layout area needed for arranging and wiring the function cells of the core is increased.
In other words, the automatic arranging and wiring method of the related art 1 has not only the above-explained drawback, namely the repetition of layout designing, but also the following drawback. That is, as shown in FIG. 2B, all of the interface function cells 18 are arranged adjacent to the boundary line 12 of the core. Since all of the interface function cells 18 are concentrated to the outermost portion of the core, the peripheral length of the core is extended. As a result, the dimension of the core is increased and an occupied area by the core is increased.
Also, in the automatic arranging and wiring method of the related art 2, since the virtual block 32 is occupies as a portion of the core, the occupied area by the core is similarly increased.
In order to solve the above-explained drawback, the following solution may be conceived in the automatic arranging and wiring method of the related art 1. That is, the interface function cells 18 are arranged not only at the position adjacent to the boundary line 12, but also inside the boundary line 12. However, when this alternative structure is employed, the internal wiring lines 17 of the core are concentrated in the inner side of the boundary line 12 such that the wiring region K cannot be reserved, and therefore the repetitions of the layout designing works are increased.
Japanese Laid Open Patent Application, (JPA-Heisei 5-267454) discloses the below-mentioned pattern data producing method for the core. This pattern data producing method is comprised of the following steps (a) to (f). At the step (a), the virtual terminal position Ts is set to the grid position G fitted to the technology of the chip 19 to be mounted with respect to the terminal position Ta of the core pattern 20 outside the core pattern 20 formed by another technology, which does not depend upon the technology for the chip 19. At the step (b), the wiring pattern La is formed which connects the terminals Ta and Ts each other. At the step (c), a new terminal position Tn is set to the grid position G fitted to the technology for the chip 19 with respect to the virtual position Ts. At the step (d), the wiring pattern Ln is formed which connects the virtual terminal position Ts to the new terminal position Tn. At the step (e), the above-described wiring patterns La and Ln are added to the core pattern 20 to form the new pattern data. At the step (f), this newly added pattern data is used as the pattern data P of the new core fitted to the technology for the chip 19 to be mounted.
However, this conventional pattern data producing method of the core merely contributes shortening of the automatic layout processing time, but cannot solve the above-explained problems belonging to the related art 1 and also the related art 2.
The present invention is made to solve the above-described problems in the related arts as mentioned above.
An object of the present invention is to provide a semiconductor device arranging and wiring method, and also a semiconductor device arranging and wiring apparatus which can omit the step of confirming interference occurred in wiring patterns inside/outside function blocks.
Another object of the present invention is to provide a semiconductor device arranging and wiring method, and also a semiconductor device arranging and wiring apparatus in which a region used to arrange external wiring lines connected to external circuits outside a core can be reserved between the boundary line of the core and the terminal of the interface function cell, automatically.
Still another object is to provide a semiconductor device arranging and wiring method, and also a semiconductor device arranging and wiring apparatus in which can avoid a repetition of a layout designing work.
Further another object is to provide a semiconductor device arranging and wiring method, and also a semiconductor device arranging and wiring apparatus in which the problem can be solved that a layout area needed for arranging/wiring the function cells of the core is increased.
Yet still another object is to provide a semiconductor device arranging and wiring method, and also a semiconductor device arranging and wiring apparatus in which the problem can be solved that the dimension of the core is increased.
In order to achieve an aspect of the present invention, a method of producing a core for a semiconductor device includes the steps of providing a virtual block, which has a contact to be connected to an external wiring line of an external circuit outside the core, setting a wiring prohibition region in the virtual block, connection of an internal wiring line arranged inside the core to the contact being prohibited in the wiring prohibition region and arranging at least the contact of the virtual block inside the core.
In this case, the step of setting the wiring prohibition region includes setting the wiring prohibition region to have a substantially U-shaped contour, and to be opened along one direction of an omnidirectional direction outside the contact.
Also, the method of producing the core further includes the step of automatically arranging and wiring the core containing the contact to produce layout data of the core.
Further, the method of producing the core further includes the step of deleting data corresponding to the virtual block from the layout data to produce arranging and wiring data of the core.
In this case, the step of producing the layout data includes executing an automatic arranging and wiring operation of the core based upon circuit data indicative of a circuit specification of the semiconductor device, and the circuit data contains data indicative of the virtual block.
In order to achieve another aspect of the present invention, the step of producing the layout data includes executing an automatic arranging and wiring operation of the core such that the internal wiring line does not pass through the wiring prohibition region.
In order to achieve still another aspect of the invention, a method of producing a core which constitutes a semiconductor device, includes the steps of setting a boundary line of the core, providing a virtual block, setting a contact to the virtual block, the contact being used to be connected to an external wiring line of external circuit outside the core, and arranging the virtual block such that the contact is arranged inside the boundary line and on a position adjacent to the boundary line.
In this case, the step of setting the contact includes setting the contact in an edge portion of the virtual block.
Also, the step of providing the virtual block includes providing the virtual block to have a dimension equal to that of a single cell corresponding to a minimum unit of a function cell for constituting the core.
Further, the method of producing the core further includes the step of automatically arranging and wiring the core containing the contact to produce layout data of the core.
In this case, the method of producing the core further includes the step of deleting data corresponding to the virtual block from the layout data to produce arranging and wiring data of the core.
Also, the step of producing the layout data may include executing an automatic arranging and wiring operation of the core based upon circuit data indicative of a circuit specification of the semiconductor device, and the circuit data contains data indicative of the virtual block.
Further, the circuit data may contain data indicating that the virtual block has a dimension of a single cell corresponding to a minimum unit of a function cell for constituting the core.
In this case, the step of producing the layout data may include executing an automatic arranging and wiring operation of the core such that the internal wiring line does not pass through a region provided between the boundary line and the contact.
In order to achieve still another aspect of the present invention, a method of producing a core for a semiconductor device includes the step of setting a boundary line of the core, providing a virtual block, which has a contact to be connected to an external wiring line of an external circuit outside the core, setting a wiring prohibition region in the virtual block, connection of an internal wiring line arranged inside the core to the contact being prohibited in the wiring prohibition region, and arranging the virtual block such that the contact is arranged inside the boundary line, and on a position adjacent to the boundary line.
In order to achieve yet still another aspect of the present invention, a semiconductor device producing apparatus for producing a core for a semiconductor device includes unit for providing a virtual block, which has a contact to be connected to an external wiring line of an external circuit outside the core, unit for setting a wiring prohibition region in the virtual block, connection of an internal wiring line arranged inside the core to the contact being prohibited in the wiring prohibition region, and unit for arranging at least the contact of the virtual block inside the core.
In this case, the unit for setting the wiring prohibition region sets the wiring prohibition region to have a substantially U-shaped contour, and to be opened along one direction of an omnidirectional direction outside the contact.
Also, in this case, the semiconductor device producing apparatus, further includes unit for automatically arranging and wiring the core containing the contact to produce layout data of the core.
Further, the semiconductor device producing apparatus further includes unit for deleting data corresponding to the virtual block from the layout data to produce arranging and wiring data of the core.
In this case, the unit for producing the layout data executes an automatic arranging and wiring operation of the core based upon circuit data indicative of a circuit specification of the semiconductor device, and the circuit data contains data indicative of the virtual block.
Also, the unit for producing the layout data executes an automatic arranging and wiring operation such that the internal wiring line does not pass through the wiring prohibition region.
In this case, the unit for arranging the virtual block arranges the virtual block on a position corresponding to an external contact formed in the external circuit and used to be connected with the contact.
Also, the unit for arranging the virtual block arranges the virtual block between an external contact formed in the external circuit and used to be connected with the contact, and a function cell to be an interface of the core as a part of the core.
In order to achieve another aspect of the present invention, a semiconductor device producing apparatus for producing a core for a semiconductor device, includes unit for setting a boundary line of the core, unit for providing a virtual block, unit for setting a contact to the virtual block, wherein the contact is used to be connected to an external wiring line of an external circuit outside the core, and unit for arranging the virtual block such that the contact is arranged inside the boundary line and on a position adjacent to the boundary line.
In order to achieve still another aspect of the present invention, the unit for setting the contact sets the contact in an edge portion of the virtual block.
In this case, the unit for providing the virtual block provides the virtual block to have a dimension equal to that of a single cell corresponding to a minimum unit of a function cell for constituting the core.
Also, the semiconductor device producing apparatus, further includes unit for automatically arranging and wiring the core containing the contact to produce layout data of the core.
Further, the semiconductor device producing apparatus, further includes unit for deleting data corresponding to the virtual block from the layout data to produce arranging and wiring data of the core.
In this case, the unit for producing the layout data executes an automatic arranging and wiring operation of the core based upon circuit data indicative of a circuit specification of the semiconductor device, and the circuit data contains data indicative of the virtual block.
Also, the circuit data contains data indicating that the virtual block has a dimension equal to that of a single cell corresponding to a minimum unit of a function cell for constituting the core.
Further, the unit for producing the layout data executes an automatic arranging and wiring operation of the core such that an internal wiring line arranged inside the core does not pass through a region provided between the boundary line and the contact.
In this case, the unit for arranging the virtual block arranges the virtual block on a position corresponding to an external contact formed in the external circuit and used to be connected with the contact.
Also, the unit for arranging the virtual block arranges the virtual block between an external contact formed in the external circuit and used to be connected with the contact,and a function cell to be an interface of the core as a part of the core.
In order to achieve further another aspect of the present invention, a semiconductor device producing apparatus for producing a core for a semiconductor device, includes unit for setting a boundary line of the core, unit for providing a virtual block, which has a contact to be connected to an external wiring line of an external circuit outside the core, unit for setting a wiring prohibition region in the virtual block, connection of an internal wiring line arranged inside the core to the contact being prohibited in the wiring prohibition region, and unit for arranging the virtual block such that the contact is arranged inside the boundary line and on a position adjacent to the boundary line.